The present exemplary embodiments pertain to self-aligned vias in an interconnect structure and, more particularly, relate to self-aligned vias which are aligned to a bottom wiring line.
Via alignment to a wiring line is critical to the integrity of a semiconductor chip. As semiconductor device dimensions get smaller, via alignment becomes more difficult. In the past, there were redundant vias but in newer technologies such as in 14 nanometer (nm) technologies and below, the number of redundant vias are substantially reduced.
To solve the problem of via alignment, the vias may be made bigger to make alignment easier. However, with the above newer technologies, enlarging the vias may no longer be possible due to shorting concerns with neighbor vias and wiring lines.